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Cortex A7 A9 Comparison Essay

The ARM Cortex-A9 MPCore is a 32-bitprocessor core licensed by ARM Holdings implementing the ARMv7-A architecture. It is a multicore processor providing up to 4 cache-coherent cores.[1]

Overview[edit]

Main article: Comparison of ARMv7-A cores

Key features of the Cortex-A9 core are:[2]

  • Out-of-orderspeculative issuesuperscalar execution 8-stage[3]pipeline giving 2.50 DMIPS/MHz/core.
  • NEONSIMD instruction set extension performing up to 16 operations per instruction (optional).
  • High performance VFPv3 floating point unit doubling the performance of previous ARM FPUs (optional).
  • Thumb-2 instruction set encoding reduces the size of programs with little impact on performance.
  • TrustZone security extensions.
  • Jazelle DBX support for Java execution.
  • Jazelle RCT for JIT compilation.
  • Program Trace Macrocell and CoreSight Design Kit for non-intrusive tracing of instruction execution.
  • L2 cache controller (0–4 MB).
  • Multi-core processing.

ARM states that the TSMC 40G hard macro implementation typically operating at 2 GHz; a single core (excluding caches) occupies less than 1.5 mm2 when designed in a TSMC 65 nanometer (nm) generic process[4] and can be clocked at speeds over 1 GHz, consuming less than 250 mW per core.[5]

Chips[edit]

Several system on a chip (SoC) devices implement the Cortex-A9 core, including:

  • Altera SoC FPGA[6]
  • AMLogic AML8726-M[7]
  • Apple A5, A5X
  • Broadcom BCM11311 (Persona ICE)[8]
  • Calxeda EnergyCore ECX-1000[9]
  • Entropic EN7588[10]
  • NXP Semiconductors (Formerly Freescale)QorIQ Layerscape LS1024A [11]
  • Freescale Semiconductori.MX6[12]
  • HiSilicon[13] K3V2 -Hi3620[14]
  • Marvell Avastar 88W8787, used in the Sony PlayStation Vita[15][16]
  • MediaTek MT6575[17] (single core), MT6577[18] (dual core)
  • Mindspeed Technologies Mindspeed Comcerto 2000[19][20][21]
  • Nufront NuSmart 2816, 2816M, 115[22]
  • NvidiaTegra 2 (without NEON extensions), Tegra 3 and Tegra 4i
  • Trident Microsystems 847x/8x/9x SoC family[23]
  • Renesas Electronics RZ/A1H,M,L,LU Family
  • Samsung Exynos 4210,[24] 4212, 4412, 4415
  • Rockchip RK3066,[25] RK292x, RK31xx
  • STMicroelectronics SPEAr1310,[26] SPEAr1340[27]
  • ST-Ericsson Nova A9500, NovaThor U8500,[28]NovaThor U9500[29]
  • Texas InstrumentsOMAP4 processors
  • Texas InstrumentsSitara AM437x[30]
  • WonderMedia WM8850, WM8950 and WM8980[31]
  • Xilinx Extensible Processing Platform[32]
  • ZiiLABS ZMS-20[33]

Systems on a chip[edit]

This list is incomplete; you can help by expanding it.

Development platforms[edit]

This list is incomplete; you can help by expanding it.

DeveloperNameSoCRAMFlashSDSATAUSBEthernetWi-FiBluetoothOther
MYIRMYD-AM437XTexas Instruments Sitara AM437x512MB DDR34GB eMMCSD Card4 x USB2.0 Host +1 x USB 2.0 Device2 x 10/100/1000M-bit Ethernet2 x Camera, HDMI, LCD/TSP
MYIRMYD-C7Z010/20Xilinx XC7Z010/201GB DDR34GB eMMCSD Card4 x USB2.0 Host10/100/1000M-bit Ethernet3 x PMoD, 1 x FMC,1 xSFP
BoardconEM4418

MINI4418

Samsung S5P44181GB DDR34GB eMMC1 SD/MMC2 x USB 2.0 Host + 1 x USB 2.0 OTG10/100/1000M-bit Ethernet MAC(RTL8211E-VB-CG)802.11b/g/nBluetooth4.0GPS,3G
FriendlyARMNanoPi-2[47]

NanoPi-2 Fire[48] NanoPi M2[49] NanoPC-T2[50]

Samsung S5P441832bit 1GB DDR38GB on PC-T22 microSD ports2.0 USB port/sRTL8211E on NanoPi-2 Fire, M2, PC-T2.802.11b/g/nBT 4.0 Dual mode40 RasberryPi compatible GPIO pins, UART, very small size and cost.
OrigenboardOrigenboard[51]Samsung Exynos 42101 GiB DDR32 port SD/MMCembeddedSWB-A31SWB-A31
OdroidOdroid-X[52]Samsung Exynos 44122 GiB LPDDR2-800SDHC + eMMC module socket (non-standard)6×USB 2.0 host + micro-USB 2.0 device10/100 Mbit/s
OdroidOdroid-U3[53]Samsung Exynos 44122 GBeMMC module socket (non-standard), microSD3×USB 2.0 host + micro-USB 2.0 device/host10/100 Mbit/sHardkernel has other product variants using the 4412. USB supports external Notebook harddrive with no external power. Preloaded emmc with Android and LUbuntu available.[54]
PandaBoardPandaBoardTI OMAP4430[55]1 GiB LPDDR2SD/MMCLAN9514-JZXLAN9514-JZXLS240-WI-01-A20LS240-WI-01-A20
Calao systemsSnowball[56]ST-Ericsson Nova A9500[57]1 GiB LPDDR24/8 GB eMMCmicroSDFT232RLAN9221AW-NH580AW-NH580GPS, accelerometer, magnetometer, gyroscope, barometer
Trim-SliceTrim-Slice[58]Tegra 2 series1 GiB DDR2-667SDHC + microSDHCGL830embeddedRTL8111DLRT3070
RadxaRadxa Rock[59]Rockchip RK31882 GiB DDR3-8008 GBmicroSDXC2×USB 2.0 host + micro-USB 2.0 device10/100 Mbit/s150 Mbit/s 802.11b/g/nBluetooth 4.0
TOPICMiami/Florida[60]Xilinx xc7z0301 GiB DDR3L256Mb NOR 1Gb NANDmicroSD2x (FPGA)USB 2.0 OTG10/100/1000 Mbit/s802.11b/g/nSingle chip CPU/FPGA module. HDMI-in/out, PMOD, 4x serial.

See also[edit]

References[edit]

  1. ^"ARM Cortex-A9 MPCore". Arm.com. Retrieved 2012-02-02. 
  2. ^"Cortex-A9 Processor Specifications". ARM. 
  3. ^"White paper: The ARM Cortex-A9 Processors"(PDF). ARM. Archived from the original(PDF) on 17 November 2014. 
  4. ^"Cortex-A9 Single Core Processor". Arm.com. Retrieved 2012-02-02. 
  5. ^"ARM spins multicore-enabled Cortex core - News - Linux for Devices". 
  6. ^SoC FPGA overview, Altera 
  7. ^Mobile Internet Devices, Amlogic, archived from the original on 4 May 2014 
  8. ^"BCM11311 - Persona ICE Application Processor". Broadcom. 
  9. ^ ab"EnergyCore™ ECX-1000: Technical Specifications". Calxeda. Retrieved 2012-05-08. 
  10. ^"High Performance, Dual-Core IP Set-top Box SoC". Entropic. 
  11. ^QorIQ® Layerscape 1024A Dual-Core Communications Processor, NXP Semiconductors 
  12. ^"Introducing the i.MX 6 Series". Freescale Semiconductor. 
  13. ^http://www.hisilicon.com
  14. ^"HiSilicon Unveils Quad-Core Cortex A9 K3V2 Processor (Hi3620)". 
  15. ^Johnny Cullen (24 January 2011). "Sony outs tech specs for NGP". VG247. Retrieved 25 January 2011. 
  16. ^"Sony Playstation Vita Teardown & Product Analysis". TechInsights. Retrieved 2013-10-15. 
  17. ^ ab"MediaTek - MT6575". MediaTek. 
  18. ^ ab"MediaTek - MT6577". MediaTek. 
  19. ^Roy Rubenstein (9 October 2012). "An ARM based programmable processor is set to enable new communications products". 
  20. ^Kevin Trosian (8 January 2013). "Mindspeed to Showcase the Industry's First ARM Cortex A9-based Communications Processor with Integrated DPI at 2013 CES". 
  21. ^"MACOM to Showcase Newly Acquired Mindspeed Comcerto 2000 System-on-Chip (SoC) Processors at the 2014 International CES". 7 January 2014. 
  22. ^"Computer System Chip". Nufront. 
  23. ^NXP to show the first fully integrated 45nm set top box soc based on ARM cortex - A9 processors 
  24. ^"Exynos 4210". samsung.com. 2012-01-20. Retrieved 2012-02-02. 
  25. ^ abRK3066 Dual-Core Era is coming 
  26. ^SPEAr1310 Dual-core Cortex A9 embedded MPU for communications 
  27. ^SPEAr1340 Dual-core Cortex A9 embedded MPU for communications 
  28. ^ST-Ericsson NovaThor U8500, ST-Ericsson, archived from the original on 22 July 2013, retrieved 19 February 2011 
  29. ^ST-Ericsson NovaThor U9500, ST-Ericsson, archived from the original on 2 October 2011, retrieved 25 September 2011 
  30. ^"AM437x Sitara Processors". 
  31. ^ ab"WonderMedia Announces PRIZM WM8950 with Android 4.0 Support". 19 May 2013. Retrieved 2013-06-17. 
  32. ^White Paper: Extensible Processing Platform(PDF) 
  33. ^ZiiLABS ZMS-20 Dual ARM Cortex A9 Media Processor 
  34. ^Introducing the i.MX 6 Series of Applications Processors(PDF) 
  35. ^Vivante GPU IP Cores Power the Latest Freescale i.MX 6 Series of Application Processors 
  36. ^Nufront 2GHz ARM Cortex-A9 for Desktop, Laptop and Netbook – NuSmart 2816 
  37. ^RZ A1H Home 
  38. ^RZ A1M Home 
  39. ^RZ A1L Home 
  40. ^RZ A1L, Home 
  41. ^http://www.gizmochina.com/2012/12/05/review-of-rockchip-rk3166-quad-core-chipset/
  42. ^SPEAr family of embedded microprocessors(PDF) 
  43. ^PNX8473 
  44. ^PNX8483 
  45. ^PNX849x [dead link][dead link]
  46. ^http://www.xilinx.com/products/silicon-devices/epp/zynq-7000/index.htm
  47. ^NanoPi-2 wiki 
  48. ^NanoPi-2 Fire wiki 
  49. ^NanoPi M2 wiki 
  50. ^NanoPC-T2 wiki 
  51. ^OriginBoard Documents 
  52. ^Open Exynos4 Quad Mobile Development Platform 
  53. ^Odroid U3 Platform 
  54. ^Odroid Store 
  55. ^OMAP 4 Platform: OMAP4430/OMAP4460 
  56. ^Snowball technical documentation, archived from the original on 2011-07-15 
  57. ^Changing the game: ST-Ericsson Unveils NovaThor Family of Smartphone Platforms Combining its Most Advanced Application Processors with the Latest Generation of Modems 
  58. ^Trim-Slice Models 
  59. ^Radxa Rock specification 
  60. ^Topic Embedded Products Boards 

External links[edit]

ARM Holdings
Other

"ARM8" redirects here. For the ARMv8-A architecture, see ARMv8-A. For the ARMv8-R architecture, see ARMv8-R.

This is a list of microarchitectures based on the ARM family of instruction sets designed by ARM Holdings and 3rd parties, sorted by version of the ARM instruction set, release and name. ARM provides a summary of the numerous vendors who implement ARM cores in their design.[1]Keil also provides a somewhat newer summary of vendors of ARM based processors.[2] ARM further provides a chart[3] displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM core families.

ARM cores[edit]

Designed by ARM[edit]

ARM familyARM architectureARM coreFeatureCache (I / D), MMUTypical MIPS @ MHzReference
ARM1ARMv1ARM1First implementationNone
ARM2ARMv2ARM2ARMv2 added the MUL (multiply) instructionNone4 MIPS @ 8 MHz
0.33 DMIPS/MHz
ARMv2aARM250Integrated MEMC (MMU), graphics and I/O processor. ARMv2a added the SWP and SWPB (swap) instructionsNone, MEMC1a7 MIPS @ 12 MHz
ARM3ARMv2aARM3First integrated memory cache4 KB unified12 MIPS @ 25 MHz
0.50 DMIPS/MHz
ARM6ARMv3ARM60ARMv3 first to support 32-bit memory address space (previously 26-bit).
ARMv3M first added long multiply instructions (32x32=64).
None10 MIPS @ 12 MHz
ARM600As ARM60, cache and coprocessor bus (for FPA10 floating-point unit)4 KB unified28 MIPS @ 33 MHz
ARM610As ARM60, cache, no coprocessor bus4 KB unified17 MIPS @ 20 MHz
0.65 DMIPS/MHz
[4]
ARM7ARMv3ARM7008 KB unified40 MHz
ARM710As ARM700, no coprocessor bus8 KB unified40 MHz[5]
ARM710aAs ARM7108 KB unified40 MHz
0.68 DMIPS/MHz
ARM7TARMv4TARM7TDMI(-S)3-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bitaddressingNone15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz
ARM710TAs ARM7TDMI, cache8 KB unified, MMU36 MIPS @ 40 MHz
ARM720TAs ARM7TDMI, cache8 KB unified, MMU with FCSE (Fast Context Switch Extension)60 MIPS @ 59.8 MHz
ARM740TAs ARM7TDMI, cacheMPU
ARM7EJARMv5TEJARM7EJ-S5-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructionsNone
ARM8ARMv4ARM8105-stage pipeline, static branch prediction, double-bandwidth memory8 KB unified, MMU84 MIPS @ 72 MHz
1.16 DMIPS/MHz
[6][7]
ARM9TARMv4TARM9TDMI5-stage pipeline, ThumbNone
ARM920TAs ARM9TDMI, cache16 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension)200 MIPS @ 180 MHz[8]
ARM922TAs ARM9TDMI, caches8 KB / 8 KB, MMU
ARM940TAs ARM9TDMI, caches4 KB / 4 KB, MPU
ARM9EARMv5TEARM946E-SThumb, enhanced DSP instructions, cachesVariable, tightly coupled memories, MPU
ARM966E-SThumb, enhanced DSP instructionsNo cache, TCMs
ARM968E-SAs ARM966E-SNo cache, TCMs
ARMv5TEJARM926EJ-SThumb, Jazelle DBX, enhanced DSP instructionsVariable, TCMs, MMU220 MIPS @ 200 MHz
ARMv5TEARM996HSClockless processor, as ARM966E-SNo caches, TCMs, MPU
ARM10EARMv5TEARM1020E6-stage pipeline, Thumb, enhanced DSP instructions, (VFP)32 KB / 32 KB, MMU
ARM1022EAs ARM1020E16 KB / 16 KB, MMU
ARMv5TEJARM1026EJ-SThumb, Jazelle DBX, enhanced DSP instructions, (VFP)Variable, MMU or MPU
ARM11ARMv6ARM1136J(F)-S8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructionsVariable, MMU740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz[9]
ARMv6T2ARM1156T2(F)-S9-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructionsVariable, MPU[10]
ARMv6ZARM1176JZ(F)-SAs ARM1136EJ(F)-SVariable, MMU + TrustZone965 DMIPS @ 772 MHz, up to 2,600 DMIPS with four processors[11]
ARMv6KARM11MPCoreAs ARM1136EJ(F)-S, 1–4 core SMPVariable, MMU
SecurCoreARMv6-MSC0000.9 DMIPS/MHz
ARMv4TSC100
ARMv7-MSC3001.25 DMIPS/MHz
Cortex-MARMv6-MCortex-M0[12]Microcontroller profile, most Thumb + some Thumb-2,[13] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryOptional cache, no TCM, no MPU0.84 DMIPS/MHz
Cortex-M0+[14]Microcontroller profile, most Thumb + some Thumb-2,[13] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions0.93 DMIPS/MHz
Cortex-M1[15]Microcontroller profile, most Thumb + some Thumb-2,[13] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memoryOptional cache, 0–1024 KB I-TCM, 0–1024 KB D-TCM, no MPU136 DMIPS @ 170 MHz,[16] (0.8 DMIPS/MHz FPGA-dependent)[17]
ARMv7-MCortex-M3[18]Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions1.25 DMIPS/MHz
ARMv7E-MCortex-M4[19]Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memoryOptional cache, no TCM, optional MPU with 8 regions1.25 DMIPS/MHz (1.27 w/FPU)
Cortex-M7[20]Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision FPU, hardware multiply and divide instructions0−64 KB I-cache, 0−64 KB D-cache, 0–16 MB I-TCM, 0–16 MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions2.14 DMIPS/MHz
Cortex-RARMv7-RCortex-R4[21]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 8/12 regions
Cortex-R5[22]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP)[23]0–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. MPU with 12/16 regions
Cortex-R7[24]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP[23]0–64 KB / 0–64 KB, ? of 0–128 KB TCM, opt. MPU with 16 regions
Cortex-R8[25]TBDTBD
Cortex-A
(32-bit)
ARMv7-ACortex-A5[26]Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)4−64 KB / 4−64 KB L1, MMU + TrustZone1.57 DMIPS/MHz per core
Cortex-A7[27]Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, architecture and feature set are identical to A15, 8–10 stage pipeline, low-power design[28]8−64 KB / 8−64 KB L1, 0–1 MB L2, MMU + TrustZone1.9 DMIPS/MHz per core
Cortex-A8[29]Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline16–32 KB / 16–32 KB L1, 0–1 MB L2 opt. ECC, MMU + TrustZoneUp to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)
Cortex-A9[30]Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-orderspeculative issuesuperscalar, 1–4 SMP cores, MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)16–64 KB / 16–64 KB L1, 0–8 MB L2 opt. parity, MMU + TrustZone2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual-core)
Cortex-A12[31]Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-orderspeculative issuesuperscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)32−64 KB3.0 DMIPS/MHz per core
Cortex-A15[32]Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-orderspeculative issuesuperscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline[28]32 KB w/parity / 32 KB w/ECC L1, 0–4 MB L2, L2 has ECC, MMU + TrustZoneAt least 3.5 DMIPS/MHz per core (up to 4.01 DMIPS/MHz depending on implementation)[33]
Cortex-A17[34]Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / integer divide / fused MAC / Jazelle RCT / hardware virtualization, out-of-orderspeculative issuesuperscalar, 1–4 SMP cores, MPCore, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP32 KB L1, 256 KB–8 MB L2 w/optional ECC2.8 DMIPS/MHz
ARMv8-ACortex-A32[35]Application profile, AArch32, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline8–64 KB w/optional parity / 8−64 KB w/optional ECC L1 per core, 128 KB–1 MB L2 w/optional ECC shared
Cortex-A
(64-bit)
ARMv8-ACortex-A35[36]Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–1 MB L2 shared, 40-bit physical addresses1.78 DMIPS/MHz
Cortex-A53[37]Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline8−64 KB w/parity / 8−64 KB w/ECC L1 per core, 128 KB–2 MB L2 shared, 40-bit physical addresses2.3 DMIPS/MHz
Cortex-A57[38]Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-way superscalar, deeply out-of-order pipeline48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses4.1 - 4.5 DMIPS/MHz[39][40]
Cortex-A72[41]Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-way superscalar, deeply out-of-order pipeline48 KB w/DED parity / 32 KB w/ECC L1 per core; 512 KB–2 MB L2 shared w/ECC; 44-bit physical addresses4.7 DMIPS/MHz
Cortex-A73[42]Application profile, AArch32 and AArch64, 1–4 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 2-way superscalar, deeply out-of-order pipeline64 KB / 32−64 KB L1 per core, 256 KB–8 MB L2 shared w/ optional ECC, 44-bit physical addresses4.8 DMIPS/MHz[43]
ARMv8.2-ACortex-A55[44]Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, triple issue, in-order pipeline[45]64 / 64 kB L1, 256 kB L2 per core, 4 MB L3 shared
Cortex-A75[46]Application profile, AArch32 and AArch64, 1–8 SMP cores, TrustZone, NEON advanced SIMD, VFPv4, hardware virtualization, 3-way superscalar, deeply out-of-order pipeline[47]64 / 64 kB L1, 512 kB L2 per core, 4 MB L3 shared
ARM familyARM architectureARM coreFeatureCache (I / D), MMUTypical MIPS @ MHzReference

As Dhrystone is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution.

Designed by third parties[edit]

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

Core FamilyInstruction setMicroarchitectureFeatureCache (I / D), MMUTypical MIPS @ MHz
StrongARM
(Digital)
ARMv4SA-1105-stage pipeline16 KB / 16 KB, MMU100–206 MHz
1.0 DMIPS/MHz
SA-1100derivative of the SA-11016 KB / 8 KB, MMU
Faraday[48]
(Faraday Technology)
ARMv4FA5106-stage pipelineUp to 32 KB / 32 KB cache, MPU1.26 DMIPS/MHz
100–200 MHz
FA526Up to 32 KB / 32 KB cache, MMU1.26 MIPS/MHz
166–300 MHz
FA6268-stage pipeline32 KB / 32 KB cache, MMU1.35 DMIPS/MHz
500 MHz
ARMv5TEFA606TE5-stage pipelineNo cache, no MMU1.22 DMIPS/MHz
200 MHz
FA626TE8-stage pipeline32 KB / 32 KB cache, MMU1.43 MIPS/MHz
800 MHz
FMP626TE8-stage pipeline, SMP1.43 MIPS/MHz
500 MHz
FA726TE13 stage pipeline, dual issue2.4 DMIPS/MHz
1000 MHz
XScale
(Intel / Marvell)
ARMv5TEXScale7-stage pipeline, Thumb, enhanced DSP instructions32 KB / 32 KB, MMU133–400 MHz
BulverdeWireless MMX, wireless SpeedStep added32 KB / 32 KB, MMU312–624 MHz
Monahans[49]Wireless MMX2 added32 KB / 32 KB L1, optional L2 cache up to 512 KB, MMUUp to 1.25 GHz
Sheeva
(Marvell)
ARMv5Feroceon5–8 stage pipeline, single-issue16 KB / 16 KB, MMU600–2000 MHz
Jolteon5–8 stage pipeline, dual-issue32 KB / 32 KB, MMU
PJ1 (Mohawk)5–8 stage pipeline, single-issue, Wireless MMX232 KB / 32 KB, MMU1.46 DMIPS/MHz
1.06 GHz
ARMv6 / ARMv7-APJ46–9 stage pipeline, dual-issue, Wireless MMX2, SMP32 KB / 32 KB, MMU2.41 DMIPS/MHz
1.6 GHz
Snapdragon
(Qualcomm)
ARMv7-AScorpion[50]1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide)256 KB L2 per core2.1 DMIPS/MHz per core
Krait[50]1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide)4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core3.3 DMIPS/MHz per core
ARMv8-AKryo[51]4 cores. ?Up to 2.2 GHz

(6.3 DMIPS/MHz)

Ax
(Apple)
ARMv7-ASwift[52]2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEONL1: 32 KB / 32 KB, L2: 1 MB3.5 DMIPS/MHz per core
ARMv8-ACyclone[53]2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64L1: 64 KB / 64 KB, L2: 1 MB, L3: 4 MB1.3–1.4 GHz
ARMv8-ATyphoon[53][54]2 or 3 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64L1: 64 KB / 64 KB, L2: 1 or 2 MB, L3: 4 MB1.4−1.5 GHz
ARMv8-ATwister[55]2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON / TrustZone / AArch64L1: 64 KB / 64 KB, L2: 2 MB, L3: 4 MB or 0 MB1.85 or 2.26 GHz
ARMv8-AHurricane[56]2 or 3 cores. AArch64, 6-decode, 6-issue, 9-wide, superscalar, out-of-orderL1: 64 KB / 64 KB, L2: 3 or 8 MB, L3: 4 or 0 MB2.34 or 2.38 GHz
X-Gene
(Applied Micro)
ARMv8-AX-Gene64-bit, quad issue, SMP, 64 cores[57]Cache, MMU, virtualization3 GHz (4.2 DMIPS/MHz per core)
Denver
(Nvidia)
ARMv8-ADenver[58][59]2 cores. AArch64, 7-wide superscalar, in-order, dynamic code optimization, 128 MB optimization cache,
Denver1: 28nm, Denver2:16nm
128 KB I-cache / 64 KB D-cacheUp to 2.5 GHz
Carmel
(Nvidia)
ARMv8(t.b.d.)Carmel[60][61]2 cores. AArch64, 10-wide superscalar, in-order, dynamic code optimization, ? MB optimization cache,
functional safety, dual execution, parity & ECC
 ? KB I-cache / ? KB D-cacheUp to ? GHz
ThunderX
(Cavium)
ARMv8-AThunderX64-bit, with two models with 8–16 or 24–48 cores (×2 w/two chips) ?Up to 2.2 GHz
K12
(AMD)
ARMv8-AK12[62] ? ? ?
Exynos
(Samsung)
ARMv8-AM1 ("Mongoose")[63]4 cores. AArch64, 8-wide, quad-issue, superscalar, out-of-order64 KB I-cache / 32 KB D-cache, L2: 16-way shared 2 MB5.1 DMIPS/MHz

(2.6 GHz)

ARM core timeline[edit]

The following table lists each core by the year it was announced.[64][65] Cores before ARM7 are not included.

YearClassic coresCortex cores
ARM7ARM8ARM9ARM10ARM11MicrocontrollerReal-timeApplication
(32-bit)
Application
(64-bit)
1993ARM700
1994ARM710
ARM7DI
ARM7TDMI
1995ARM710a
1996ARM810
1997ARM710T
ARM720T
ARM740T
1998ARM9TDMI
ARM940T
1999ARM9E-S
ARM966E-S
2000ARM920T
ARM922T
ARM946E-S
ARM1020T
2001ARM7TDMI-S
ARM7EJ-S
ARM9EJ-S
ARM926EJ-S
ARM1020E
ARM1022E
2002ARM1026EJ-SARM1136J(F)-S
2003ARM968E-SARM1156T2(F)-S
ARM1176JZ(F)-S
2004Cortex-M3
2005ARM11MPCoreCortex-A8
2006ARM996HS
2007Cortex-M1Cortex-A9
2008
2009Cortex-M0Cortex-A5
2010Cortex-M4(F)Cortex-A15
2011Cortex-R4
Cortex-R5
Cortex-R7
Cortex-A7
2012Cortex-M0+Cortex-A53
Cortex-A57
2013Cortex-A12
2014Cortex-M7(F)Cortex-A17
2015Cortex-A35
Cortex-A72
2016Cortex-M23
Cortex-M33(F)
Cortex-R8
Cortex-R52
Cortex-A32Cortex-A73
2017Cortex-A55
Cortex-A75

See also[edit]

References[edit]

  1. ^"ARM Powered Standard Products"(PDF). 2005. Retrieved 23 December 2017. 
  2. ^ARM Ltd and ARM Germany GmbH. "Device Database". Keil. Retrieved 6 January 2011. 
  3. ^"Processors". ARM. 2011. Retrieved 6 January 2011. 
  4. ^"ARM610 Datasheet". ARM Holdings. August 1993. Archived from the original(PDF) on July 3, 2016. Retrieved July 5, 2017. 
  5. ^"ARM710 Datasheet". ARM Holdings. July 1994. Archived from the original(PDF) on July 3, 2016. Retrieved July 5, 2017. 
  6. ^ARM Holdings (7 August 1996). "ARM810 – Dancing to the Beat of a Different Drum"(PDF). Hot Chips. Retrieved 21 September 2013. 
  7. ^"VLSI Technology Now Shipping ARM810". EE Times. 26 August 1996. Retrieved 21 September 2013. 
  8. ^Register 13, FCSE PID register ARM920T Technical Reference Manual
  9. ^"ARM1136J(F)-S – ARM Processor". Arm.com. Archived from the original on 21 March 2009. Retrieved 18 April 2009. 
  10. ^https://www.arm.com/products/processors/classic/arm11/arm1156.php
  11. ^"ARM11 Processor Family". ARM. Retrieved 12 December 2010. 
  12. ^Cortex-M0 Specification Summary; ARM Holdings.
  13. ^ abcCortex-M0/M0+/M1 Instruction set; ARM Holding.[permanent dead link]
  14. ^Cortex-M0+ Specification Summary; ARM Holdings.
  15. ^Cortex-M1 Specification Summary; ARM Holdings.
  16. ^"ARM Extends Cortex Family with First Processor Optimized for FPGA" (Press release). ARM Holdings. 19 March 2007. Retrieved 11 April 2007. 
  17. ^"ARM Cortex-M1". ARM product website. Retrieved 11 April 2007. 
  18. ^Cortex-M3 Specification Summary; ARM Holdings.
  19. ^Cortex-M4 Specification Summary; ARM Holdings.
  20. ^Cortex-M7 Specification Summary; ARM Holdings.
  21. ^Cortex-R4 Specification Summary; ARM Holdings.
  22. ^Cortex-R5 Specification Summary; ARM Holdings.
  23. ^ abCortex-R5 & Cortex-R7 Press Release; ARM Holdings; 31 January 2011.
  24. ^Cortex-R7 Specification Summary; ARM Holdings.
  25. ^Cortex-R8 Specification Summary; ARM Holdings.
  26. ^Cortex-A5 Specification Summary; ARM Holdings.
  27. ^Cortex-A7 Specification Summary; ARM Holdings.
  28. ^ ab"Deep inside ARM's new Intel killer". The Register. 20 October 2011. 
  29. ^Cortex-A8 Specification Summary; ARM Holdings.
  30. ^Cortex-A9 Specification Summary; ARM Holdings.
  31. ^Cortex-A12 Summary; ARM Holdings.
  32. ^Cortex-A15 Specification Summary; ARM Holdings.
  33. ^Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9 | ITProPortal.com
  34. ^Cortex-A17 Specification Summary; ARM Holdings.
  35. ^"Cortex-A32 Processor". ARM Holdings. Retrieved 18 May 2016. 
  36. ^"Cortex-A35 Processor". ARM Holdings. Retrieved 18 May 2016. 
  37. ^"Cortex-A53 Processor". ARM Holdings. Retrieved 13 October 2012. 
  38. ^"Cortex-A57 Processor". ARM Holdings. Retrieved 13 October 2012. 
  39. ^"Cortex-Ax vs performance". Retrieved 5 May 2017. 
  40. ^"Relative Performance of ARM Cortex-A 32-bit and 64-bit Cores". Retrieved 5 May 2017. 
  41. ^"Cortex-A72 Processor". ARM Holdings. Retrieved 3 February 2015. 
  42. ^"Cortex-A73 Processor". ARM Holdings. Retrieved 2 June 2016. 
  43. ^"Cortex-Ax vs performance". Retrieved 5 May 2017. 
  44. ^Ltd., Arm. "Cortex-A55 – Arm Developer". ARM Developer. Retrieved 2017-11-27. 
  45. ^"Hardware.Info Nederland". nl.hardware.info (in Dutch). Retrieved 2017-11-27. 
  46. ^Ltd., Arm. "Cortex-A75 – Arm Developer". ARM Developer. Retrieved 2017-11-27. 
  47. ^"Hardware.Info Nederland". nl.hardware.info (in Dutch). Retrieved 2017-11-27. 
  48. ^"Processor Cores". Faraday Technology. 
  49. ^"3rd Generation Intel XScale Microarchitecture: Developer's Manual"(PDF). download.intel.com. Intel. May 2007. Retrieved 2 December 2010. 
  50. ^ abQualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored; Anandtech.
  51. ^"Snapdragon 820 and Kryo CPU: heterogeneous computing and the role of custom compute". Qualcomm. 2015-09-02. Retrieved 2015-09-06. 
  52. ^Lal Shimpi, Anand (15 September 2012). "The iPhone 5's A6 SoC: Not A15 or A9, a Custom Apple Core Instead". AnandTech. Retrieved 15 September 2012. 
  53. ^ abSmith, Ryan (November 11, 2014). "Apple A8X's GPU - GAX6850, Even Better Than I Thought". Anandtech. 
  54. ^Chester, Brandon (July 15, 2015). "Apple Refreshes The iPod Touch With A8 SoC And New Cameras". Anandtech. Retrieved September 11, 2015. 
  55. ^Ho, Joshua (September 28, 2015). "iPhone 6s and iPhone 6s Plus Preliminary Results". Anandtech. Retrieved December 18, 2015. 
  56. ^Ho, Joshua (September 28, 2015). "The iPhone 7 and iPhone 7 Plus Review". Anandtech. Retrieved September 14, 2017. 
  57. ^http://www.pcworld.com/article/2464600/appliedmicros-64core-chip-could-spark-off-arm-core-war.html
  58. ^http://www.anandtech.com/Gallery/Album/3847
  59. ^http://blogs.nvidia.com/blog/2014/08/11/tegra-k1-denver-64-bit-for-android/
  60. ^https://www.golem.de/news/nvidia-drive-xavier-fuer-autonome-autos-wird-ausgeliefert-1801-132035.html
  61. ^https://wccftech.com/nvidia-drive-xavier-soc-detailed/
  62. ^http://www.anandtech.com/show/7990/amd-announces-k12-core-custom-64bit-arm-design-in-2016
  63. ^"Samsung Announces Exynos 8890 with Cat.12/13 Modem and Custom CPU". AnandTech. 
  64. ^ARM Company Milestones.
  65. ^ARM Press Releases.

Further reading[edit]

See also: List of books about ARM Cortex-M

Application ARM-based chips

Application
processors
(32-bit)
Cortex-A5
Cortex-A7
  • Allwinner A2x, A3x, A83T, H3, H8
  • Freescale i.MX7
  • Broadcom VideoCore BCM2836, BCM23550
  • Freescale QorIQ LS10xx
  • Leadcore LC1813, LC1860/C, LC1913, LC1960
  • Marvell Armada PXA1920, 1500 mini plus
  • MediaTek MT65xx
  • Qualcomm Snapdragon200, 400
Cortex-A8
Cortex-A9
  • Actions ATM702x, ATM703x
  • Altera Cyclone V, Arria V/10
  • Amlogic AML8726, MX, M6x, M801, M802/S802, S812, T86x
  • Apple A5, A5X
  • Broadcom VideoCore BCM21xxx, BCM28xxx
  • Freescale i.MX6
  • HiSilicon K3V2, 910's
  • InfoTM iMAPx912
  • Leadcore LC1810, LC1811
  • Marvell Armada 1500 mini
  • MediaTek MT65xx
  • Nvidia Tegra, 2, 3, 4i
  • Nufront NuSmart 2816M, NS115, NS115M
  • Renesas EMMA EV2, R-Car H1, RZ/A
  • Rockchip RK292x, RK30xx, RK31xx
  • Samsung Exynos 4 421x, 441x
  • ST-Ericsson NovaThor
  • Telechips TCC8803
  • Texas Instruments OMAP 4
  • Texas Instruments Sitara AM4xxx
  • VIA WonderMedia WM88x0, 89x0
  • Xilinx Zynq-7000
  • ZiiLABS ZMS-20, ZMS-40
Cortex-A15

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